… d3 d2 d1 d0 Rise_delay = 1 NS
.model xormod d_xor ( Fall_delay = 1 NS
+ rise_delay=10n fall_delay=8n)
Model Name Example Description Parameter Defaults
Buffer abuffer din dout buf_mod Output = Input Rise_delay = 1 NS
.model buf_mod d_buffer ( Fall_delay = 1 NS
+ rise_delay=10n fall_delay=8n)
Inverter ainvert din dout inv Output = ~Input Rise_delay = 1 NS
.model inv d_inverter ( Fall_delay = 1 NS
+ rise_delay=10n fall_delay=10n)
And and [d3 d2 d1 d0] dout amod Output = dn … d3 d2 d1 d0 Rise_delay = 1 NS
.model amod d_and ( Fall_delay = 1 NS
+ rise_delay=10n fall_delay=8n)
Nand anand [d3 d2 d1 d0] dout nmod Output = ~(dn … d3 d2 d1 d0) Rise_delay = 1 NS
.model nmod d_nand ( Fall_delay = 1 NS
+ rise_delay=10n fall_delay=8n)
Or aor [d3 d2 d1 d0] dout ormod Output = dn + … + d3 + d2 + d1 + d0 Rise_delay = 1 NS
.model ormod d_or ( Fall_delay = 1 NS
+ rise_delay=10n fall_delay=8n)
Nor anor [d3 d2 d1 d0] dout normod Output = ~(dn + … + d3 + d2 + d1 + d0) Rise_delay = 1 NS
.model normod d_nor ( Fall_delay = 1 NS
+ rise_delay=10n fall_delay=8n)
Xor axor [d3 d2 d1 d0] dout xormod Output = dn
Xnor axnor [d3 d2 d1 d0] dout xnormod Output = ~(dn
Tristate at din en dout trimod Output = Input when Enable = ONE Delay = 1 NS
.model trimod d_tristate (delay=8n)Output = HIZ when Enable = ZERO
Pullup apu dout pumod Output = ONE
.model pumod d_pullup
Pulldown apd dout pdmod Output = ZERO
.model pdmod d_pulldown
D Flip Flop adff data clk set reset q qb dffmoddata clk set reset q qb Clk_delay = 1 NS
.model dffmod d_dff ( x x 1 0 1 0 Set_delay = 1 NS
+ clk_delay=10n set_delay=8n x x 0 1 0 1 Reset_delay = 1 NS
+ reset_delay=8n rise_delay=5n 1 
0 0 1 0 Rise_delay = 1 NS
+ fall_delay=5n ic=1) 0 0 0 0 1 Fall_delay = 1 NS
IC = 0
JK Flip Flop ajk j k clk set reset q qb tmod j k clk set reset q qb Clk_delay = 1 NS
.model tmod d_tff ( x x x 1 0 1 0 Set_delay = 1 NS
+ clk_delay=10n set_delay=8n x x x 0 1 0 1 Reset_delay = 1 NS
+ reset_delay=8n rise_delay=5n 1 0 0 0 1 0 Rise_delay = 1 NS
+ fall_delay=5n ic=2) 0 0 0 0 0 1 Fall_delay = 1 NS
Toggle Flip Flop at t clk set reset q qb jkmod t clk set reset q qb Clk_delay = 1 NS
.model jkmod d_tff ( x x 1 0 1 0 Set_delay = 1 NS
+ clk_delay=10n set_delay=8n x x 0 1 0 1 Reset_delay = 1 NS
+ reset_delay=8n rise_delay=5n 1 0 0 qb q Rise_delay = 1 NS
+ fall_delay=5n ic=2) 0 0 0 q qb Fall_delay = 1 NS
S-R Flip Flop asr s r clk set reset q qb srmod s r clk set reset q qb Clk_delay = 1 NS
.model srmod d_srff ( x x x 1 0 1 0 Set_delay = 1 NS
+ clk_delay=10n set_delay=8n x x x 0 1 0 1 Reset_delay = 1 NS
+ reset_delay=8n rise_delay=5n 0 0 0 0 q qb Rise_delay = 1 NS
+ fall_delay=5n ic=2) 0 1 0 0 0 1 Fall_delay = 1 NS
1 0 0 0 1 0
D Latch ad d en set reset q qb dlmod d en set reset q qb Data_delay = 1 NS
.model dlmod d_dlatch ( x x 1 0 1 0 Enable_delay = 1 NS
+ data_delay=10n enable_delay=8n x x 0 1 0 1 Set_delay = 1 NS
+ set_delay=8n reset_delay=5n 0 0 0 0 q qb Reset_delay = 1 NS
+ rise_delay=5n fall_delay=5n ic=2) 0 1 0 0 0 1 Rise_delay = 1 NS
1 1 0 0 1 0 Fall_delay = 1 NS
S-R Latch asr s r en set reset q qb srmod s r en set reset q qb SR_delay = 1 NS
.model srmod d_srlatch ( x x x 1 0 1 0 Enable_delay = 1 NS
+ sr_delay=10n enable_delay=8n x x x 0 1 0 1 Set_delay = 1 NS
+ set_delay=8n reset_delay=5n x x 0 0 0 q qb Reset_delay = 1 NS
+ rise_delay=5n fall_delay=5n ic=2) 0 0 1 0 0 q qb Rise_delay = 1 NS
0 1 1 0 0 0 1 Fall_delay = 1 NS
1 0 1 0 0 1 0
State Machine as [d2 d1 d0] clk reset [y1 y0] A file is read which describes a digital state state_file = state.txt
state machine. The file syntax: Clk_delay = 1 NS
.model state d_state ( 1. A comment line has an “*” in column 1. Reset_delay = 1 NS
+ state_file=counter.txt 2. A line having only whitespace does nothing.
+ clk_delay=5n reset_delay=5n) 3. A state description line having 5 fields:
state number (example: “1”)
outputs for the state (example: “0s 0s
1s”)
inputs for the state (example: “1 0 1”)
transition characters (examples:
“->”, “:”)
next state number (example: “5”)
4. A partial state description line that is a
continuation of the previous state, and
has 3
fields:
inputs for the state (example: “1 0 1”)
transition characters (examples:
“->”, “:”)
next state number (example: “5”)
Frequency Divider afd f_in f_out fdiv A programmable frequency divider where the Div_factor = 2
.model fdiv d_fdiv ( divisor is div_factor and the duty cycle is High_cycles = 1
+ div_factor=4 high_cycles=3 controlled by high_cycles. I_count initializes I_count = 0
+ i_count=2 the counting sequence. The frequency is Rise_delay = 1 NS
+ rise_delay=5n fall_delay=5n) determined by the rising edge of the input Fall_delay = 1 NS
pulse.
Digital Source ads [d2 d1 d0] dsource A file is read which describes a digital input_file = source.txt
.model dsource d_source ( source.
+ input_file=source.txt) The file syntax:
1. A comment line has an “*” in column 1.
2. A line having only whitespace does nothing.
3. A line whose first token is time, and the
succeeding tokens are the values for the
outputs at that time. Example:
* Time Clock Reset
0.0 0s 1s
10.0n 0s 0s
20.0n 1s 0s
30.0n 0s 0s
RAM aram32x4 [di3 di2 di1 di0] A RAM function having data inputs, data Select_value = 1
+ [do3 do2 do1 do0] outputs, address, write enable and chip select Ic = 2
+ [a4 a3 a2 a1 a0] as Read_delay = 0.1US
+ write_en select ram I/O. The width of the RAM is determined by the
.model ram d_ram (select_value=3 number of data inputs/outputs. The depth of
+ ic=0 read_delay=10n) the
RAM is determined by the number of address
bits. IC is the initial state of the RAM.
Current Limiter a1 [inp inm] vdd vee out climit Models the effects of an Operational Amplifier in_offset = 0.0 V
.model climit ilimit (in_offset=1m or Comparator. The following parameters are gain = 1.0
+ gain=1 r_out_source=100 used for smoothing between discontinuous regions r_out_source = 1.0 Ohm
+ r_out_sink=100 of operation: v_pwr_range, i_source_range, r_out_sink = 1.0 Ohm
+ i_limit_source=10m i_sink_range and r_out_domain. i_limit_source = 0.0 A
+ i_limit_sink=15m i_limit_sink = 0.0 A
+ v_pwr_range=10u v_pwr_range = 1.0 mV
+ i_source_range=10n i_source_range = 1.0 nA
+ i_sink_range=10n i_sink_range = 1.0 nA
+ r_out_domain=100n) r_out_domain=1e-9ohm
Slew Rate Block asr in out slew The output is a copy of the input except that Rise_slope = 1.0 g V/S
.model slew slew (rise_slope=1G both the positive and negative slew rates are Fall_slope = 1.0 g V/S
+ fall_slope=1G range=0.1) limited. Range = 0.1 V
The range parameter is used for smoothing the
output between discontinuous regions of
operation.
Controlled Sine Wave as cntl_in output sine The frequency of the output sine wave is Cntl_array = 0.0 V
Oscillator .model sine sine ( determined by indexing the input voltage into Freq_array = 1k Hz.
+ cntl_array=[-1 0 5 6] the cntl_array. Linear interpolation is Out_low = -1.0 V
+ freq_array=[10 10 1000 1000] performed between points in the cntl and freq Out_high = 1.0 V
+ out_low=-5.0 out_high=5.0) arrays.
Controlled Triangle at cntl_in output triangle The frequency of the output triangle wave is Cntl_array = 0.0 V
Wave Oscillator .model triangle triangle ( determined by indexing the input voltage into Freq_array = 1k Hz.
+ cntl_array=[-1 0 5 6] the cntl_array. Linear interpolation is Out_low = -1.0 V
+ freq_array=[10 10 1000 1000] performed between points in the cntl and freq Out_high = 1.0 V
+ out_low=-5.0 out_high=5.0 arrays. rise_duty = rise_time / period. Rise_duty = 0.5
+ rise_duty=0.9)
Controlled Square asq cntl_in output triangle The frequency of the output square wave is Cntl_array = 0.0 V
Wave Oscillator .model triangle triangle ( determined by indexing the input voltage into Freq_array = 1k Hz.
+ cntl_array=[-1 0 5 6] the cntl_array. Linear interpolation is Out_low = -1.0 V
+ freq_array=[10 10 1000 1000] performed between points in the cntl and freq Out_high = 1.0 V
+ out_low=-5.0 out_high=5.0 arrays. Duty_cycle = Duty_cycle = 0.5
+ duty_cycle=0.9 rise_time=1u (rise_time+fall_time+high_time) / period. Rise_time = 1.0 nS
+ fall_time=1u) Fall_time = 1.0 nS
Controlled One-Shot a1 cntl_in clock output 1shot The width of the output pulse is determined by Cntl_array = 0.0 V
.model 1shot oneshot ( indexing the input voltage into the cntl_array. Pw_array = 1.0 uS
+ cntl_array=[-1 0 10 11] Linear interpolation is performed between points Out_low = 0.0 V
+ pw_array=[1u 1u 0.1m 0.1m] in the cntl and pw arrays. Duty_cycle = Out_high = 1.0 V
+ clk_trig=0.9 (rise_time+fall_time+high_time) / period. Delay = 1.0 nS
+ pos_edge_trig=FALSE Rise_time = 1.0 nS
+ out_low=-5.0 out_high=5.0 Fall_time = 1.0 nS
+ delay=0.9u rise_time=1u
+ fall_time=1u)
N-bit Comparator a1 [a2 a1 a0] [b2 b1 b0] agtb aeqb Compares to input vectors A and B. One of the Rise_delay = 1.0 nS
+ agtb comp output signals (agtb, aeqt, agtb) goes low Fall_delay = 1.0 nS
.model comp d_comp ( depending on the result of the comparison.
+ rise_delay=0.9u fall_delay=1u)
N-bit Counter a1 reset in [b2 b1 b0] count Reset high will reset the output vector. In Rise_delay = 1.0 nS
.model count d_count ( going high increments the counter by 1. Fall_delay = 1.0 nS
+ rise_delay=0.9u fall_delay=1u)
N-bit Decoder a1 [a1 a0] [b3 b2 b1 b0] strobe The value of the A input vector determines Rise_delay = 1.0 nS
+ decode which B output vector goes low. If Strobe =. Fall_delay = 1.0 nS
.model decode d_decoder ( high, then the B vector goes high
+ rise_delay=0.9u fall_delay=1u)
N-bit Full Adder a1 [a1 a0] [b1 b0] clk mode [y1 y0]Adds the A and B vectors when the clock goes Rise_delay = 1.0 nS
+ carry_out fadder high. Mode = high indicates the full adder Fall_delay = 1.0 nS
.model fadder d_fadder ( operates asynchronously, independent of the
+ rise_delay=0.9u fall_delay=1u) value of clock
N-bit Multiplier a1 [a1 a0] [b1 b0] clk mode Multiplies the A and B vectors when the clock Rise_delay = 1.0 nS
+ [y3 y2 y1 y0] mult goes high. Mode = high indicates the multiplier Fall_delay = 1.0 nS
.model mult d_mult ( operates asynchronously, independent of the
+ rise_delay=0.9u fall_delay=1u) value of clock
N-1 Multiplexer a1 [a3 a2 a1 a0] out [s1 s0] strb If Strb =. high, then out goes low. Rise_delay = 1.0 nS
mux Fall_delay = 1.0 nS
.model mux d_mux (
+ rise_delay=0.9u fall_delay=1u)
N-bit Shift Registera1 [a3 a2 a1 a0] clr s1 s0 clk clr s1 s0 clk Y Rise_delay = 1.0 nS
+ [y3 y2 y1 y0] shift 0 x x 1 0 Fall_delay = 1.0 nS
.model shift d_shift ( 1 x x 0 Y
+ rise_delay=0.9u fall_delay=1u) 1 1 1 A
1 0 1 RightShift
1 1 0 LeftShift
1 0 0 x Y