A mixed analog and digital model is a model that contains both analog and digital functionality. These models have both analog and digital I/O, and are called from both the traditional portion of SPICE and from the digital event loop.
Model Name Example Description Parameter Defaults
N - N Analog to adc [a1 a2] [d1 d2] adcmod Converts the voltage on the analog input node in_low = 0.0 V
Digital Converter .model adcmod adc_bridge ( a[i] to the corresponding digital level for in_high = 1.0 V
+ in_low=1.0 in_high=2.0 digital output node d[i]. rise_delay = 1.0 NS
+ rise_delay=50n fall_delay=20n) fall_delay = 1.0 NS
N - N Digital to adac [d1] [a1] dacmod Converts the digital level for digital input out_low = 0.0 V
Analog Converter .model dacmod dac_bridge ( node d[i] to the corresponding voltage on the out_high = 1.0 V
+ in_low=1.0 in_high=2.0 analog output node a[i] t_rise = 1.0 NS
+ t_rise=50n t_fall=20n) t_fall = 1.0 NS
1 - N Analog to a2d ain clk [d3 d2 d1 d0] adcmod Converts the voltage on the analog input node analog_low = 0.0 V
Digital Converter .model adcmod a2d_converter ( to the corresponding digital levels for digital analog_high = 1.0 V
+ analog_low=1.0 analog_high=2.0 output nodes d[i] on the rising edge of the rise_delay = 1.0 NS
+ rise_delay=50n fall_delay=20n) clock input. fall_delay = 1.0 NS
N - 1 Digital to ad2a [d7 d6 d5 d4 d3 d2 d1 d0] aout Converts the digital levels for digital input analog_low = 0.0 V
Analog Converter dacmod nodes d[i] to a corresponding voltage on the analog_high = 1.0 V
.model dacmod d2a_converter ( analog output. slew_rate = 2.0 V/uS
+ analog_low=1.0 analog_high=2.0
+ slew_rate=5k)
Controlled Digital a5 analog_in digital_out var_clk Converts the voltage on the analog input node Cntl_array = 0.0 V
Oscillator .model var_clk d_osc ( into a digital oscillator. A linear Freq_array = 1.0 Meg Hz
+ cntl_array = [-2 -1 1 2] interpolation is performed on the voltage Duty_cycle = 0.5
+ freq_array = [1k 1k 10k 10k] control array and the corresponding frequency is Init_phase = 0 Degree
+ duty_cycle = 0.4 init_phase=180 found in the frequency array. Rise_delay = 1 NS
+ rise_delay = 10n fall_delay=8n) Fall_delay = 1 NS