Convergence in a DC or Transient Analysis
When performing DC analysis, SPICE programs sometimes run into convergence problems as they try to solve the DC matrix on the different nodes of the circuit.
Both DC and transient solutions are obtained by an iterative process that terminates when both of the following conditions hold:
1. The non-linear branch currents converge to within a tolerance of RELTOL (default = 0.1%) or ABSTOL (default = 1 pA), whichever is larger.
2. The node voltages converge to within a tolerance of RELTOL (default = 0.1%) or VNTOL (default = 1 mV), whichever is larger.
To help achieve convergence on problematic circuits, DR. SPICE incorporates two algorithms that enhance DC convergence: GMIN stepping and DC source ramping. If DR. SPICE fails to converge using the standard methods, it starts the GMIN stepping algorithm. If this algorithm fails, DR. SPICE applies the DC source ramping algorithm.
Although the algorithms used in DR. SPICE have been found to be very reliable, on rare occasions, some analyses may fail to converge to a solution. When this failure occurs, DR. SPICE terminates the job.
Failure to converge in DC analysis is usually due to an error in specifying circuit connections, element values, or model parameter values. Regenerative switching circuits or circuits with positive feedback probably will not converge in the DC analysis unless the OFF option is used for some of the devices in the feedback path, or the .NODESET statement is used to force the circuit to converge to the desired state.
A small amount of conductance (default = 10-12) is added between each node and ground. The option GMIN controls the value: increasing GMIN helps you find a DC solution.
When convergence fails, DR. SPICE informs the user where the non-convergence occurred in the DR. SPICE output file and where to manually set proper initial conditions on the diverging nodes to reach convergence. To set initial conditions on the nodes, refer to ‘‘Setting Transient Initial Conditions (.IC)” later in this section.
GMIN Stepping:
Using this algorithm, DR. SPICE automatically adds a small conductance from every node of the circuit to ground, then calculates the DC solution. When a solution is reached, DR. SPICE decreases the value of that conductance, then uses the solution as an initial guess to obtain the next solution. The process repeats until a proper DC solution is reached with a minimum GMIN value (default = 10-12).
DC Source Ramping:
If GMIN stepping fails, DR. SPICE automatically starts this algorithm. During DC source ramping, all DC sources are set to zero, then gradually ramped to their desired values. As DR. SPICE incrementally ramps the values, it simultaneously calculates the DC solution for the circuit and applies it as an initial condition for the next iteration.
GEAR Integration:
The default DR. SPICE integration method is Trapezoidal. However, for some circuits, Trapezoidal integration will cause false oscillations or non-convergence during the transient analysis.
Setting the option [method = GEAR] (refer to Options forces DR. SPICE to use the Gear integration method, which has the effect of filtering out the oscillations.
The dynamic timestep control algorithm is dependent upon the integration method being used and can affect whether a transient simulation converges. Some circuits may converge when using Gear integration, whereas these circuits do not converge using Trapezoidal integration.
NOTE: Use Gear integration as a last resort. Using Gear integration will cause your simulation times to increase.
SaveBias and LoadBias:
Although use of GMIN stepping and DC source ramping often leads to proper DC convergence, their use may also slow down the simulation. (Transient analysis will not start until a proper DC solution on the circuit is reached.) Once a proper DC solution is reached, you can avoid this delay every time the circuit is rerun. DR. SPICE provides a way to save all the initial conditions in a file (SaveBias function) then reload them whenever another run is requested (LoadBias function). For more information about these functions, refer to the .SaveBias and .LoadBias statements.
NOTE: When the UIC option is used in the .TRANS analysis command card, DR. SPICE skips the DC analysis stage, and thereby avoids running either convergence method.